1. Field of the Invention
The present invention relates to a two-level translation lookaside buffer (TLB), and more particularly, to a two-level TLB having a first level TLB on the CPU and a second level TLB residing in otherwise unused portions of the cache tag RAMs.
2. Description of the Prior Art
Conventional computer processing systems frequently include a very large main memory address space that a user accesses via virtual memory addresses. These virtual memory addresses are typically converted to physical memory addresses by any of a number of techniques so that the processor can access the desired information stored in the main memory. However, since access to the main memory is often quite time consuming, many computer systems employ a cache memory for interfacing the main memory to the processor. The cache memory typically includes the memory pages and associated tags most likely to be asked for by the processor, and since the cache memory is typically small and located proximate the processor, it can be accessed much faster than the main memory. Cache memories thus help to significantly improve processing speed for typical applications.
Certain conventional cache memories comprise a high speed data Ram and a parallel high speed tag RAM. The address of each entry in the cache is generally the same as the low order portion of the main memory address to which the entry corresponds, where the high order portion of the main memory address is stored in the tag RAM as tag data. Thus, if main memory has 2.sup.m blocks of 2.sup.n words each, the i'th word in the cache data RAM will be a copy of the i'th word of one of the 2.sup.m blocks in main memory, and the identity of that block is stored in the tag RAM. Then, when the processor requests data from memory, the low order portion of the address is supplied as an address to both the cache data and tag RAMs. The tag for the selected cache entry is compared with the high order portion of the processor's address and, if it matches, the data from the cache data RAM is enabled onto the data bus. If the tag does not match the high order portion of the processor's address, then the data is fetched from main memory. The data is also placed in the cache for potential future use, overwriting the previous entry. On a data write from the processor, either the cache RAM or main memory or both may be updated, and flags such as "data valid" and "data dirty" may be used to indicate to one device that a write has occurred in the other. The use of such a small, high speed cache in the computer design permits the use of relatively slow but inexpensive RAM for the large main memory space without sacrificing processing speed.
An address translation unit is used in conjunction with cache memories in such virtual memory systems for performing the aforementioned virtual to physical address translation. Generally, the address translation unit provides a map to the desired page of main memory, and such a map is typically stored as a page table. To increase the speed of access to entries in the page table, and hence the speed of address translation, translation lookaside buffers (TLBs) are often employed with or in place of the page tables. TLBs generally operate as caches for the page table and, when used, allow faster access to the page tables. The TLBs, as with the data caches, are typically small and may be located proximate to or actually on the processor chip. The speed of the processor can thus be improved without significantly increasing its chip area. A conventional address translation system is described, for example, by Moussouris et al in U.S. Pat. No. 4,953,073.
Most existing reduced instruction set computer (RISC) designs use only a single level TLB. However, one known design implements a second-level TLB in the cache data array in order to take advantage of the system clock frequencies available with modern VLSI technologies. For example, in the MIPS RC6280 CPU, the primary cache is split between instructions and data, is direct mapped, virtually addressed, and write through. The second level cache is unified, two-way set associative, physically addressed, and copy back. The principal tags for the second level cache are virtual, rather than physical, so as to facilitate a small on-chip TLB. The CPU chip contains the virtual address generation logic which forms the index into the primary cache, a 96-bit first level TLB which is used to form the index into the second level cache, and the cache control state machines which handle the management of the cache subsystem and memory mapping functions.
The MIPS RC6280 CPU utilizes a two-level TLB so that the address translation may be provided on-chip. The first level TLB comprises a 16-entry, 96-bit "TLB-slice" located on the CPU chip, while the second level TLB backs up the first level TLB with a 4,096-entry full TLB stored in the second level cache. The TLB-slice consists of two direct mapped tables (one for instructions, one for data) which deliver just enough bits of the physical page number to complete the second level cache index. On the other hand, the second-level TLB is disposed in a reserved section of the second level cache in order to simplify TLB miss software. However, by implementing the second-level TLB in the cache data array in this manner, the maximum amount of cache data memory available is thereby limited. Of course, this adversely affects system performance.
Accordingly, it is desired to design a two-level TLB so that address translation may be performed on-chip without limiting the maximum amount of cache data memory available. The present invention has been designed to meet this need.